The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
Apr. 30, 2008
David B. Bowler, Acton, MA (US);
James M. Aufiero, Reading, MA (US);
Francis J. Calabresi, Harvard, MA (US);
Christopher J. Pekalsky, Raymond, NH (US);
David B. Bowler, Acton, MA (US);
James M. Aufiero, Reading, MA (US);
Francis J. Calabresi, Harvard, MA (US);
Christopher J. Pekalsky, Raymond, NH (US);
ARRIS Enterprises, Inc., Suwanee, GA (US);
Abstract
An optical network terminal is provided for use in a passive optical network (PON). The optical network terminal includes a data port for receiving data packets from an external device and a processor for converting the data packets to data link frames. In addition, the optical network terminal includes a memory configured to store a time division multiplexing scheme identifying a time slot assigned to each of a plurality of network nodes in the PON for transmission of upstream optical signals. An optical transceiver is provided for converting the data link frames to upstream optical signals and transmitting the optical signals on an upstream TDMA (time division, multiple access) channel to an Optical Line Terminal (OLT). The optical transceiver includes a burst mode laser diode for generating the optical signals and a burst mode laser driver for biasing the laser diode with a bias signal and a modulation bias signal. The laser driver includes a dual closed loop feedback control circuit. The dual closed loop feedback control circuit is configured to measure and adjust a logic zero output power level from the laser diode during a time slot identified from the time division multiplexing scheme stored in the memory.