The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
Jul. 24, 2014
Altera Corporation, San Jose, CA (US);
Weiqi Ding, Fremont, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A clocking arrangement for transceivers in an integrated circuit device includes a plurality of fractionally adjustable phase-locked loops. Each respective one of the fractionally adjustable phase-locked loops generates a respective transmit frequency for a respective one of the transceivers. There is a respective clock-data recovery module in a receive portion of each respective one of the transceivers, and each respective clock-data recovery module includes a respective fractionally adjustable frequency-lock loop. There is a reference clock input providing a reference clock for a plurality of the fractionally adjustable phase-locked loops and the fractionally adjustable frequency-lock loops. The reference clock input can be a sole reference clock input providing a reference clock for all of the adjustable phase-locked frequency-lock loops. Alternatively, the reference clock input can include a plurality of separate reference clock inputs, each providing a separate reference clock to a predetermined subset of the adjustable phase-locked or frequency-lock loops.