The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
Apr. 17, 2014
Applicant:
University of Macau, Taipa, Macau, CN;
Inventors:
Assignee:
UNIVERSITY OF MACAU, Taipa, Macau, CN;
Primary Examiner:
Int. Cl.
CPC ...
H01B 1/10 (2006.01); H03H 11/04 (2006.01); H04B 1/10 (2006.01); H04W 4/00 (2009.01); H04B 1/12 (2006.01); H04L 27/34 (2006.01); H04L 27/38 (2006.01); H03H 11/12 (2006.01); H03F 3/193 (2006.01); H03F 3/45 (2006.01); H03H 7/38 (2006.01);
U.S. Cl.
CPC ...
H03H 11/04 (2013.01); H03F 3/193 (2013.01); H03F 3/45183 (2013.01); H03H 11/1213 (2013.01); H04B 1/1036 (2013.01); H04B 1/123 (2013.01); H04L 27/3405 (2013.01); H04L 27/3809 (2013.01); H04W 4/008 (2013.01); H03F 2200/294 (2013.01); H03H 7/38 (2013.01); H04B 2001/1072 (2013.01);
Abstract
A complex-pole load is configured as a parallel circuit, having 4 transistors arranged in pairs. Each pair of transistors has a transistor gated by a control voltage sources, and connected in parallel with a transistor diode connected for gating by the respective input. The control voltage sources result in the circuit synthesizing a first order complex pole at a positive IF (+IF) or a negative IF (−IF) for channel selection and image rejection, offering image rejection and channel selection concurrently.