The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2016

Filed:

Oct. 29, 2015
Applicant:

Murata Manufacturing Co., Ltd., Kyoto, JP;

Inventor:

Ken Wakaki, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/04 (2006.01); H03F 1/26 (2006.01); H03G 3/10 (2006.01); H03F 1/02 (2006.01); H03F 1/22 (2006.01); H03F 3/193 (2006.01); H03F 1/32 (2006.01); H03F 1/56 (2006.01); H03F 3/195 (2006.01); H03F 3/24 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0205 (2013.01); H03F 1/0266 (2013.01); H03F 1/0272 (2013.01); H03F 1/223 (2013.01); H03F 1/226 (2013.01); H03F 1/3205 (2013.01); H03F 1/56 (2013.01); H03F 3/193 (2013.01); H03F 3/195 (2013.01); H03F 3/1935 (2013.01); H03F 3/245 (2013.01); H03F 2200/108 (2013.01); H03F 2200/222 (2013.01); H03F 2200/318 (2013.01); H03F 2200/387 (2013.01); H03F 2200/451 (2013.01); H03F 2200/516 (2013.01);
Abstract

A radio-frequency amplifier circuit includes first and second FETs cascode-connected to each other. The gate of the first FET is connected to a radio-frequency input terminal, and the drain of the second FET is connected to a radio-frequency output terminal. The source of the first FET is connected to a ground, and the drain of the first FET and the source of the second FET are connected to each other. A drive voltage is applied to the drain of the second FET. A bias setting unit is connected to the gate of the second FET. The bias setting unit sets a second control voltage to be applied to the second FET so that a node voltage between the drain of the first FET and the source of the second FET will be substantially half of the drive voltage.


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