The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
Dec. 15, 2014
Applicant:
SK Hynix Inc., Icheon, KR;
Inventor:
Seong-Hyun Kim, Icheon, KR;
Assignee:
SK HYNIX INC., Icheon, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); H01L 45/00 (2006.01); G06F 3/06 (2006.01); G06F 12/08 (2016.01); G06F 5/14 (2006.01); H01L 21/768 (2006.01); C23C 16/40 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1253 (2013.01); C23C 16/405 (2013.01); G06F 3/0617 (2013.01); G06F 3/0643 (2013.01); G06F 3/0679 (2013.01); G06F 5/14 (2013.01); G06F 12/0802 (2013.01); H01L 21/76838 (2013.01); H01L 45/1233 (2013.01); H01L 45/14 (2013.01); H01L 45/141 (2013.01); H01L 45/145 (2013.01); H01L 45/147 (2013.01); H01L 45/16 (2013.01); G06F 2205/126 (2013.01); G06F 2212/222 (2013.01);
Abstract
An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer including a hole over a substrate; a first nitride layer disposed on sidewalls of the hole; a selector disposed in a bottom portion of the hole and over the first nitride layer on the sidewalls of the hole; a stacked structure including a variable resistance pattern disposed over a lower structure including the selector; and a second nitride layer disposed in an upper portion and on sidewalls of the stacked structure.