The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
Jan. 07, 2016
Renesas Electronics Corporation, Tokyo, JP;
Ken Shibata, Kanagawa, JP;
Yuta Yanagitani, Kanagawa, JP;
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Abstract
A semiconductor device having a high degree of freedom of layout has a first part AR, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP) for the plurality of wells PW is arranged on one side so as to interpose the ARin a Y-axis direction, and a common power feeding region (ARN) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP) for the PW wells, a p-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR, and a plurality of MIS transistors are correspondingly formed.