The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2016

Filed:

Mar. 05, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Do-Yeong Lee, Gwangmyeong-Si, KR;

Chan-Sic Yoon, Anyang-Si, KR;

Ki-Seok Lee, Busan, KR;

Hyeon-Ok Jung, Daejeon, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 21/8242 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10823 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 27/10814 (2013.01); H01L 27/10855 (2013.01); H01L 27/10885 (2013.01); H01L 27/10888 (2013.01); H01L 29/4236 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening.


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