The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
Jul. 09, 2015
Applicant:
Kang Joon Lee, Hwaseong-si, KR;
Inventor:
Kang Joon Lee, Hwaseong-si, KR;
Assignee:
Samsung Electronics Co., Ltd., Gyeonggi-Do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 25/065 (2006.01); H01L 23/13 (2006.01); H01L 23/544 (2006.01); H01L 23/373 (2006.01); H01L 23/31 (2006.01); H01L 21/52 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/4853 (2013.01); H01L 21/52 (2013.01); H01L 21/565 (2013.01); H01L 23/13 (2013.01); H01L 23/3107 (2013.01); H01L 23/373 (2013.01); H01L 23/544 (2013.01); H01L 25/50 (2013.01); H01L 2223/54426 (2013.01); H01L 2225/06593 (2013.01);
Abstract
A semiconductor package including a lower package and an upper package provided may be provided. The lower package includes a lower package substrate, a lower semiconductor chip mounted thereon, and a lower mold layer provided on the lower package substrate. The upper package includes an upper package substrate and an upper semiconductor chip thereon. The lower mold layer includes a guide portion extending along a vertical direction from an edge of the lower package substrate toward the upper package.