The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2016

Filed:

Jan. 08, 2015
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Min Sang Park, Chungcheongbuk-do, KR;

Yun Bong Lee, Chungcheongbuk-do, KR;

Suk Kwang Park, Chungcheongbuk-do, KR;

Hwang Huh, Chungcheongbuk-do, KR;

Dong Wook Lee, Seoul, KR;

Myung Su Kim, Gyeonggi-do, KR;

Sung Hoon Cho, Gyeonggi-do, KR;

Sang Jo Lee, Chungcheongbuk-do, KR;

Chang Jin Sunwoo, Chungcheongbuk-do, KR;

Gil Bok Choi, Daejeon, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 11/5628 (2013.01); G11C 16/3454 (2013.01); G11C 16/3486 (2013.01); G11C 2211/5621 (2013.01); G11C 2211/5622 (2013.01);
Abstract

A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.


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