The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2016

Filed:

Nov. 19, 2013
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Reiji Mochida, Osaka, JP;

Kazuyuki Kouno, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 11/22 (2006.01); H01L 45/00 (2006.01); H01L 27/22 (2006.01); H01L 27/24 (2006.01); G11C 8/14 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 8/14 (2013.01); G11C 11/1653 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1659 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/22 (2013.01); G11C 11/2253 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/2259 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 13/0002 (2013.01); G11C 13/003 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0023 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); H01L 27/228 (2013.01); H01L 27/2436 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); G11C 2013/005 (2013.01); G11C 2013/009 (2013.01); G11C 2013/0071 (2013.01); G11C 2213/79 (2013.01); G11C 2213/82 (2013.01);
Abstract

A nonvolatile semiconductor memory device includes: a memory cell (MC) including a cell transistor (TC) and a variable resistance element (RR); a memory cell (MC) including a cell transistor (TC) and a variable resistance element (RR); a word line (WL) connected to the cell transistor (TC); a word line (WL) connected to the cell transistor (TC); a data line (SL) connecting the cell transistor (TC) and the variable resistance element (RR) to each other; and a data line (BL) connecting the variable resistance element (RR) and the cell transistor (TC) to each other.


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