The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2016

Filed:

Jun. 18, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Jae-Duk Yu, Seoul, KR;

Dong-Ku Kang, Seongnam-si, KR;

Dae-Yeal Lee, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5628 (2013.01); G11C 5/143 (2013.01); G11C 16/10 (2013.01); G11C 16/3454 (2013.01); G11C 16/3459 (2013.01);
Abstract

A semiconductor memory device is configured to perform a first verification operation by setting an initial voltage level of a verification voltage to a first voltage level and boosting the verification voltage during a first period. The semiconductor memory device includes a memory cell array that stores program data, a sensor generating sensing data, and a condition determination unit comparing the program data and the sensing data. A control logic unit includes a verification operation controller configured to selectively perform, based on a result of comparison of the program data and the sensing data, a first verification control operation for controlling a second verification operation by setting the initial voltage level to a second voltage level and boosting the verification voltage during a second period, and a second verification control operation for controlling the second verification operation by setting the initial voltage level to the first voltage level and boosting the verification voltage during the first period.


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