The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2016

Filed:

Mar. 13, 2015
Applicant:

Megachips Corporation, Osaka, JP;

Inventor:

Takao Kusano, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 3/0613 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/7208 (2013.01); Y02B 60/1225 (2013.01);
Abstract

A system-in-package semiconductor device with a CPU, a first flash memory configured to store first instructions to be executed by the CPU, and a second flash memory configured to store second instructions to be executed in accordance with a predetermined control instruction included in the first instructions. The semiconductor device determines, prior to the CPU executing the instruction, whether an instruction read out from the first flash memory is a branch instruction, and if it is determined to be the branch instruction, causes the second flash memory to perforin read-out operation using a branch destination address value indicated by the branch instruction, and if a value of a program counter of the CPU matches the branch destination address value, while the second flash memory is in a state of being ready for read-out operation in accordance with the instruction, starts reading out the second instructions from the second flash memory.


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