The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
Oct. 15, 2014
Garima Sharda, Ghaziabad, IN;
Sunny Gupta, Noida, IN;
Akshay K. Pathak, Noida, IN;
Nidhi Sinha, Noida, IN;
Garima Sharda, Ghaziabad, IN;
Sunny Gupta, Noida, IN;
Akshay K. Pathak, Noida, IN;
Nidhi Sinha, Noida, IN;
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.