The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2016

Filed:

May. 19, 2014
Applicant:

Dell Products L.p., Round Rock, TX (US);

Inventors:

Shiguo Luo, Austin, TX (US);

George Gilman Richards, III, Round Rock, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 19/15 (2006.01); G05F 1/46 (2006.01); H02M 3/158 (2006.01); G01R 19/165 (2006.01); G01R 31/327 (2006.01); G05F 1/26 (2006.01); G01R 31/40 (2014.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
G01R 19/16538 (2013.01); G01R 19/15 (2013.01); G01R 31/3277 (2013.01); G05F 1/26 (2013.01); G05F 1/46 (2013.01); H02M 3/1584 (2013.01); G01R 31/40 (2013.01); H02M 2001/0009 (2013.01); H02M 2001/0048 (2013.01); H02M 2003/1586 (2013.01);
Abstract

A method may include deactivating a switch of a measurement circuit during a measurement portion of at least one voltage regulator phase, wherein each of the at least one voltage regulator phase is integral to a voltage regulator and each of the at least one voltage regulator phase comprises a power stage. The power stage may include a high-side switch for delivering electrical current to the at least one information handling resource in conformity with a first duty cycle of the high-side switch. The power stage may also include a low-side switch for sinking electrical current to an electrical ground in conformity with a second duty cycle of the low-side switch. The method may also include measuring a voltage across a sense resistor of the measurement circuit during the measurement portion, wherein the sense resistor is coupled in parallel with non-gate terminals of the switch.


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