The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2016
Filed:
Jun. 02, 2015
Applicants:
Jingyu Kim, Asan-si, KR;
Hyun Lee, Busan, KR;
Inventors:
JinGyu Kim, Asan-si, KR;
Hyun Lee, Busan, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H05K 1/02 (2006.01); H01L 23/00 (2006.01); H01L 23/36 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H05K 1/02 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 23/36 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 24/97 (2013.01); H01L 25/105 (2013.01); H01L 23/3121 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18161 (2013.01);
Abstract
A substrate for a semiconductor package and a method for manufacturing a semiconductor package are disclosed. The substrate comprises a surface, and package unit regions arranged on the surface in a row direction to form a plurality of rows. The package unit regions of an n+1-th row are arranged offset in a row direction from the package unit regions of an n-th row. The method includes molding semiconductor chips and spaces between the substrate and the semiconductor chips on the package unit regions of the last row at substantially the same time.