The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Jul. 06, 2015
Applicants:

Sarma Vrudhula, Chandler, AZ (US);

Niranjan Kulkarni, Phoenix, AZ (US);

Inventors:

Sarma Vrudhula, Chandler, AZ (US);

Niranjan Kulkarni, Phoenix, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/094 (2006.01); G11C 7/00 (2006.01); H03K 19/003 (2006.01); G11C 7/06 (2006.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); H03K 19/00 (2006.01); H03K 19/017 (2006.01); H03K 19/096 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H03K 19/00361 (2013.01); G11C 7/065 (2013.01); G11C 11/1673 (2013.01); G11C 13/004 (2013.01); H03K 19/0027 (2013.01); H03K 19/01707 (2013.01); H03K 19/0963 (2013.01); H03K 19/215 (2013.01);
Abstract

Threshold logic elements and methods of operating the same are disclosed. In one embodiment, a threshold logic element includes a first input gate network configured to receive a first set of logical signals, a second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. In order to make the threshold logic element more robust, the differential sense amplifier is configured to feed back the differential logical output to the first input gate network and the second input gate network. By providing the differential logical output as feedback, floating node issues are avoided and the threshold logic element is more resistant to noise.


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