The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Dec. 30, 2015
Applicant:

Seoul Semiconductor Co., Ltd., Ansan-si, KR;

Inventors:

Jung Hwa Jung, Ansan-si, KR;

Hee Tak Oh, Ansan-si, KR;

Do Hyung Kim, Ansan-si, KR;

You Jin Kwon, Ansan-si, KR;

Oh Sug Kim, Ansan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 21/00 (2006.01); H01L 33/62 (2010.01); H01L 25/075 (2006.01); H01L 33/64 (2010.01); H01L 33/58 (2010.01); H01L 33/38 (2010.01); H01L 33/52 (2010.01); H01L 33/54 (2010.01); H01L 25/16 (2006.01); H01L 33/48 (2010.01);
U.S. Cl.
CPC ...
H01L 33/62 (2013.01); H01L 25/0753 (2013.01); H01L 33/382 (2013.01); H01L 33/48 (2013.01); H01L 33/52 (2013.01); H01L 33/54 (2013.01); H01L 33/58 (2013.01); H01L 33/64 (2013.01); H01L 33/642 (2013.01); H01L 25/167 (2013.01); H01L 33/486 (2013.01); H01L 2224/48227 (2013.01);
Abstract

A light-emitting diode package includes a package body and a light-emitting diode chip disposed on the package body. The package body includes upper conductive patterns disposed on an upper insulation substrate, a lower insulation substrate disposed on lower conductive patterns, and middle conductive patterns disposed between the upper insulation substrate and the lower insulation substrate. The package body also includes upper vias electrically connecting each of the upper conductive patterns to each of the middle conductive patterns, respectively, the upper vias being disposed in the upper insulation substrate, and lower vias electrically connecting each of the middle conductive patterns to each of the lower conductive patterns, respectively, the lower vias disposed in the lower insulation substrate.


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