The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Jan. 26, 2015
Applicant:

Toppan Printing Co., Ltd., Taito-ku, Tokyo, JP;

Inventor:

Kodai Murata, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/786 (2006.01); G02F 1/1362 (2006.01); H01L 51/00 (2006.01); H01L 51/05 (2006.01); H01L 27/12 (2006.01); H01L 27/28 (2006.01); H01L 21/465 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78606 (2013.01); G02F 1/1362 (2013.01); H01L 21/02282 (2013.01); H01L 21/02623 (2013.01); H01L 21/465 (2013.01); H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H01L 27/283 (2013.01); H01L 29/7869 (2013.01); H01L 51/0003 (2013.01); H01L 51/0019 (2013.01); H01L 51/0545 (2013.01); H01L 51/0097 (2013.01);
Abstract

A source electrode () and a drain electrode () are film-formed, and a semiconductor layer () is formed in a substantially stripe shape substantially parallel to the X axis direction (channel-length direction) using a coating method. Then, a protection layer () is formed in a substantially stripe shape substantially parallel to the Y axis direction (channel width direction) orthogonal to the semiconductor layer (). Then, a semiconductor layer () portion not covered with the protection layer () is removed using an organic solvent or an inorganic solvent or a mixed solution of the organic solvent and the inorganic solvent. Consequently, the semiconductor layer () and the protection layer () are formed with improved alignment accuracy, and electrical isolation between transistor elements () can be achieved with a simplified process.


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