The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Jun. 11, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Daniel Nelson Carothers, Lucas, TX (US);

Jeffrey R. Debord, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/02667 (2013.01); H01L 21/02686 (2013.01); H01L 21/76205 (2013.01); H01L 21/76278 (2013.01); H01L 21/76281 (2013.01); H01L 21/84 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02636 (2013.01);
Abstract

An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.


Find Patent Forward Citations

Loading…