The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Sep. 30, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Yoocheol Shin, Gyeonggi-do, KR;

Jaegoo Lee, Gyeonggi-do, KR;

Young-Jin Kwon, Gyeonggi-do, KR;

Jintaek Park, Gyeonggi-do, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/76802 (2013.01); H01L 27/1157 (2013.01); H01L 27/11575 (2013.01);
Abstract

A semiconductor device is provided as follows. A peripheral circuit structure is disposed on a first substrate. A cell array structure is disposed on the peripheral circuit structure. A second substrate is interposed between the peripheral circuit structure and the cell array structure. The cell array structure includes a stacked structure, a through hole and a vertical semiconductor pattern. The stacked structure includes gate electrodes stacked on the second substrate. The through hole penetrates the stacked structure and the second substrate to expose the peripheral circuit structure. The vertical semiconductor pattern is disposed on the peripheral circuit structure, filling the through hole.


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