The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2016
Filed:
Dec. 04, 2014
Cypress Semiconductor Corporation, San Jose, CA (US);
Sungkwon Lee, Saratoga, CA (US);
Roger Bettman, Los Altos, CA (US);
Sai Prashanth Dhanraj, San Jose, CA (US);
Dung Ho, Sunnyvale, CA (US);
Leo F Luquette, Jr., Monument, CO (US);
Iman Rezanezhad Gatabi, Sunnyvale, CA (US);
Andrew Walker, Mountain View, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.