The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

May. 12, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Jae Kyu Cho, Niskayuna, NY (US);

Shan Gao, Malta, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/544 (2013.01); H01L 2223/5446 (2013.01);
Abstract

Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.


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