The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Aug. 12, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Timothy M. Sullivan, Essex, VT (US);

Glen E. Richard, Burlington, VT (US);

Stephen P. Ayotte, New Haven, VT (US);

Timothy D. Sullivan, Underhill, VT (US);

Assignee:

GlobalFoundries, Inc., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76898 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/13021 (2013.01);
Abstract

Embodiments of the present disclosure provide an integrated circuit (IC) structure with a recessed solder bump area, and methods of forming the same. An IC structure according to embodiments of the present disclosure can include: a semiconductor material, wherein an upper surface of the semiconductor material includes a non-recessed area and a recessed area laterally separated from each other, the recessed area of the upper surface being shaped to receive a solder bump therein; at least one first through-semiconductor via (TSV) positioned within the semiconductor material and including an upper surface protruding from the recessed area of the semiconductor material; and a metal layer formed over the recessed area and electrically connected to the at least one first TSV.


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