The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Jul. 14, 2014
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Anthony Fai, Palo Alto, CA (US);

Nicholas C. Seroff, Los Gatos, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/552 (2006.01); H01L 25/16 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
G11C 5/06 (2013.01); G11C 5/063 (2013.01); H01L 23/5226 (2013.01); H01L 23/552 (2013.01); H01L 24/17 (2013.01); H01L 24/24 (2013.01); H01L 24/25 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 25/16 (2013.01); H01L 29/0657 (2013.01); H01L 2224/244 (2013.01); H01L 2224/245 (2013.01); H01L 2224/24051 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/24226 (2013.01); H01L 2224/2541 (2013.01); H01L 2224/25175 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/49175 (2013.01); H01L 2225/06537 (2013.01); H01L 2225/06551 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/30107 (2013.01);
Abstract

Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.


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