The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Apr. 20, 2012
Applicants:

Alper Buyuktosunoglu, White Plains, NY (US);

Philip G. Emma, Danbury, CT (US);

Allan M. Hartstein, Chappaqua, NY (US);

Michael B. Healy, White Plains, NY (US);

Krishnan Kunjunny Kailas, Tarrytown, NY (US);

Inventors:

Alper Buyuktosunoglu, White Plains, NY (US);

Philip G. Emma, Danbury, CT (US);

Allan M. Hartstein, Chappaqua, NY (US);

Michael B. Healy, White Plains, NY (US);

Krishnan Kunjunny Kailas, Tarrytown, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 15/76 (2006.01); G06F 15/173 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 15/17387 (2013.01); G06F 9/3802 (2013.01);
Abstract

Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution.


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