The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Mar. 19, 2014
Applicant:

Lenovo Enterprise Solutions (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

Brian A. Baker, Raleigh, NC (US);

Michael Decesaris, Carrboro, NC (US);

Jeffrey R. Hamilton, Pittsboro, NC (US);

Douglas W. Oliver, Round Rock, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 9/00 (2006.01); G06F 11/14 (2006.01); G06F 9/44 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1417 (2013.01); G06F 9/4401 (2013.01); G06F 9/4405 (2013.01); G06F 9/4408 (2013.01); G06F 11/008 (2013.01);
Abstract

Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit ('CPU') sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, error characteristics associated with each available CPU, wherein the error characteristics associated with each available CPU include error information for computing devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the error characteristics associated with each available CPU and a predetermined error tolerance policy, a target CPU to utilize as a boot CPU.


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