The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Mar. 14, 2013
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Michael D. Hutton, Palo Alto, CA (US);

Anargyros Krikelis, Farnham, GB;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5055 (2013.01); G06F 9/505 (2013.01); G06F 9/5033 (2013.01); G06F 9/5044 (2013.01);
Abstract

A hybrid programmable logic is described that performs packet processing functions on received data packets using programmable logic elements, and processors interleaved with the programmable logic elements. The header data may be scheduled for distribution to processing threads associated with the processors by the programmable logic elements. The processors may perform packet processing functions on the header data using both the processing threads and hardware acceleration functions provided by the programmable logic elements.


Find Patent Forward Citations

Hutton, Michael. (2016). Mapping network applications to a hybrid programmable many-core device (U.S. Patent No. 9471388). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9471388

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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