The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2016
Filed:
Jan. 31, 2014
Applicant:
Kool Chip, Inc., San Jose, CA (US);
Inventors:
Prasad Chalasani, San Jose, CA (US);
Venkata N.S.N. Rao, Fremont, CA (US);
Assignee:
SOCTRONICS, INC., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H03L 7/00 (2006.01); H03K 19/0175 (2006.01); G06F 13/38 (2006.01); H03L 7/08 (2006.01); H03L 7/093 (2006.01); H04L 7/00 (2006.01); G06F 1/28 (2006.01); G06F 1/04 (2006.01); G06F 1/10 (2006.01); H04L 25/02 (2006.01);
U.S. Cl.
CPC ...
H03L 7/00 (2013.01); G06F 1/04 (2013.01); G06F 1/10 (2013.01); G06F 1/28 (2013.01); G06F 13/385 (2013.01); H03K 19/0175 (2013.01); H03K 19/017509 (2013.01); H03L 7/0802 (2013.01); H03L 7/093 (2013.01); H04L 7/0012 (2013.01); H04L 25/028 (2013.01); H04L 25/0276 (2013.01);
Abstract
A distribution network for distributing clock and reset signals across an address macro has circuit blocks having dividers and counters, drivers connected in a balanced tree, and drivers connected in an unbalanced tree. The dividers and counters are synchronized relative to a clock signal. The drivers connected in the balanced tree distribute the clock signal synchronously to the circuit blocks. The drivers connected in the unbalanced tree distribute a reset signal to the circuit blocks. The clock signal is distributed via the balanced tree as a function of the reset signal.