The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Mar. 19, 2015
Applicant:

Ps4 Luxco S.a.r.l., Luxembourg, LU;

Inventors:

Toru Hatakeyama, Tokyo, JP;

Toru Ishikawa, Tokyo, JP;

Assignee:

PS4 LUXCO S.A.R.L., Luxembourg, LU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01); H03K 19/00 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0027 (2013.01); G11C 5/06 (2013.01); G11C 7/1087 (2013.01);
Abstract

A semiconductor device, includes an input buffer, first and second PMOS transistors serially interconnected between a first power supply node and an output node of the input buffer. First and second NMOS transistors are serially interconnected between a second power supply node and the output node of the input buffer. A replica circuit includes a third and fourth PMOS transistors serially interconnected between the first power supply node and an output node of the replica circuit. Third and fourth NMOS transistors are serially interconnected between the second power supply node and the output node of the replica circuit. The input node of the replica circuit is connected to the output node of the replica circuit and a comparison circuit compares a voltage at the output node of the replica circuit to a reference voltage.


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