The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Jan. 17, 2014
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Rahul Kumar, Jamshedpur, IN;

Manoj Kumar, Dhanbad, IN;

Gene Sheu, Taichung, TW;

Shao-Ming Yang, Taichung, TW;

Rudy Octavius Sihombing, Medan, ID;

Chia-Hao Lee, New Taipei, TW;

Shang-Hui Tu, Jhubei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/265 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/788 (2013.01); H01L 21/02252 (2013.01); H01L 21/265 (2013.01); H01L 21/26586 (2013.01); H01L 21/28273 (2013.01); H01L 21/76224 (2013.01); H01L 29/0623 (2013.01); H01L 29/0634 (2013.01); H01L 29/407 (2013.01); H01L 29/42324 (2013.01); H01L 29/66825 (2013.01);
Abstract

The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.


Find Patent Forward Citations

Kumar, Rahul. (2016). Semiconductor device and method for fabricating the same (U.S. Patent No. 9466730). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9466730

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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