The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

May. 08, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Stephen A. Fanelli, San Marcos, CA (US);

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); H01L 21/30604 (2013.01); H01L 29/66742 (2013.01);
Abstract

Bonded semiconductor device structures and device structure fabrication processes to obviate the need for SOI wafers in many device fabrication applications are disclosed. In some examples, an etch stop layer is formed in situ during fabrication of an active device structure on a bulk semiconductor wafer. The etch stop layer enables the active device structure to be separated from the bulk semiconductor wafer in a layer transfer process in which the active device structure is bonded to a handle wafer. These examples enable the production of high-performance and low-power semiconductor devices (e.g., fully or partially depleted channel transistors) while avoiding the high costs of SOI wafers. In some examples, the gate masks the etch stop layer implant in a self-aligned process to create a fully depleted channel under the gate and deeper implants in the source and drain regions without requiring a separate masking layer.


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