The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Oct. 06, 2015
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;

Inventors:

Akira Yoshioka, Ishikawa, JP;

Toru Sugiyama, Ishikawa, JP;

Yasunobu Saito, Ishikawa, JP;

Kunio Tsuda, Ishikawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01); H01L 29/205 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 29/2003 (2013.01); H01L 29/4236 (2013.01); H01L 29/66462 (2013.01); H01L 29/66734 (2013.01); H01L 29/7788 (2013.01); H01L 29/7813 (2013.01); H01L 29/7827 (2013.01); H01L 29/205 (2013.01); H01L 29/66674 (2013.01); H01L 29/66712 (2013.01);
Abstract

A semiconductor device according to one embodiment includes an n-type first GaN-based semiconductor layer, a p-type second GaN-based semiconductor layer on the first GaN-based semiconductor layer. The second GaN-based semiconductor layer includes a low impurity concentration region and a high impurity concentration region. An n-type third GaN-based semiconductor layer is provided on the second GaN-based semiconductor layer. The device includes a gate electrode being located adjacent to the third GaN-based semiconductor layer, the low impurity concentration region, and the first GaN-based semiconductor layer intervening a gate insulating film. The device includes a first electrode on the third GaN-based semiconductor layer, a second electrode on the high impurity concentration region, and a third electrode on the opposite side of the first GaN-based semiconductor layer from the second GaN-based semiconductor layer.


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