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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9466622 B1

PDFFull Text
Date of Patent:
Oct. 11, 2016

Filed:

Jan. 14, 2016

Display device comprising a thin film transistor and a storage capacitor

Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Hiroshi Shibata, Kanagawa, JP;

Atsuo Isobe, Kanagawa, JP;

Assignee:

Semiconductor Energy Laboratory Co., LTD., Kanagawa-ken, JP;

Attorneys:

Nixon Peabody LLP

Jeffrey L. Costellia

Primary Examiner:

Ngan Ngo

Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/12 (2006.01); H01L 27/32 (2006.01); G02F 1/1345 (2006.01); G02F 1/1362 (2006.01); H01L 29/786 (2006.01); G02F 1/1333 (2006.01); G02F 1/1368 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1255 (2013.01); G02F 1/1368 (2013.01); G02F 1/13454 (2013.01); G02F 1/133345 (2013.01); G02F 1/136209 (2013.01); G02F 1/136213 (2013.01); G02F 1/136227 (2013.01); G02F 1/136277 (2013.01); G02F 1/136286 (2013.01); H01L 27/12 (2013.01); H01L 27/124 (2013.01); H01L 27/1214 (2013.01); H01L 27/3244 (2013.01); H01L 27/3248 (2013.01); H01L 27/3262 (2013.01); H01L 27/3265 (2013.01); H01L 27/3276 (2013.01); H01L 29/4908 (2013.01); H01L 29/786 (2013.01); H01L 29/78633 (2013.01);
Abstract

To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.

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