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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9466620 B1

PDFFull Text
Date of Patent:
Oct. 11, 2016

Filed:

Sep. 16, 2014

Method for manufacturing array substrate, array substrate, and display device

Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Optoelectronics Technology Co., Ltd., Beijing, CN;

Inventor:

Jinzhong Zhang, Beijing, CN;

Assignees:

BOE TECHNOLOGY GROUP CO., LTD., Beijing, CN;

BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Beijing, CN;

Attorney:

Harness, Dickey & Pierce, P.L.C.

Primary Examiner:

Chuong A Luu

Assistant Examiner:

Rodolfo Fortich

Int. Cl.
CPC ...
H01L 29/24 (2006.01); H01L 27/12 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 21/3205 (2006.01); H01L 21/56 (2006.01); H01L 29/423 (2006.01); H01L 29/417 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 23/31 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1237 (2013.01); G02F 1/1362 (2013.01); H01L 21/31111 (2013.01); H01L 21/32051 (2013.01); H01L 21/32133 (2013.01); H01L 21/56 (2013.01); H01L 21/76802 (2013.01); H01L 23/3171 (2013.01); H01L 27/127 (2013.01); H01L 29/41733 (2013.01); H01L 29/42384 (2013.01); H01L 29/66765 (2013.01); H01L 29/78684 (2013.01); G02F 2001/136236 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present invention relates to the field of liquid crystal display, and provides a method for manufacturing an array substrate, the array substrate, and a display device. In the array substrate, a gate insulating layer between source and drain electrodes and a pattern of a gate electrode has a thickness greater than that of the gate insulating layer between an active layer and the pattern of the gate electrode. Due to the thick gate insulating layer between the source and drain electrodes and the pattern of the gate electrodes, the capacitance between the source and drain electrodes and the gate electrodes will be reduced.

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