The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2016
Filed:
Nov. 13, 2014
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Min Soo Kim, Gyeonggi-do, KR;
Dong Sun Sheen, Gyeonggi-do, KR;
Young Jin Lee, Gyeonggi-do, KR;
Jin Hae Choi, Gyeonggi-do, KR;
Joo Hee Han, Seoul, KR;
Sung Jin Whang, Gyeonggi-do, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 21/28 (2006.01); H01L 21/283 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/283 (2013.01); H01L 21/28282 (2013.01); H01L 21/31111 (2013.01); H01L 21/32134 (2013.01); H01L 21/32135 (2013.01); H01L 27/11556 (2013.01); H01L 29/42344 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01);
Abstract
The device includes plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.