The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Oct. 28, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Weize Chen, Phoenix, AZ (US);

Richard J De Souza, Chandler, AZ (US);

Patrice M Parris, Phoenix, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 27/115 (2006.01); H01L 27/092 (2006.01); H01L 29/51 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 21/324 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/28035 (2013.01); H01L 21/28282 (2013.01); H01L 21/324 (2013.01); H01L 21/32139 (2013.01); H01L 21/823864 (2013.01); H01L 27/0922 (2013.01); H01L 27/11573 (2013.01); H01L 29/42344 (2013.01); H01L 29/42348 (2013.01); H01L 29/511 (2013.01); H01L 29/518 (2013.01);
Abstract

A method for making a semiconductor structure includes forming an oxide layer onto non-volatile memory, high, and low voltage device regions of a substrate and forming a first gate material layer over the oxide layer. The first gate material layer is patterned to form a set of memory device select gates in the non-volatile memory device region and a set of gates in the high voltage device region. The patterning is performed while maintaining the oxide and first gate material layers over the low voltage device region. The method also includes forming a second gate material layer over the structure and forming a non-volatile storage layer between the set of select gates and the second gate material layer, from which a set of memory device control gates is patterned. Thereafter, the first gate material layer is patterned to form a set of gates in the low voltage device region.


Find Patent Forward Citations

Chen, Weize. (2016). Semiconductor structure having a dual-gate non-volatile memory device and methods for making same (U.S. Patent No. 9466608). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9466608

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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