The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9466596 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 11, 2016

Filed:

Dec. 26, 2007
Applicants:

Sehat Sutardja, Los Altos Hills, CA (US);

Ravishanker Krishnamoorthy, Singapore, SG;

Inventors:

Sehat Sutardja, Los Altos Hills, CA (US);

Ravishanker Krishnamoorthy, Singapore, SG;

Assignee:

Marvell World Trade Ltd., St. Michael, BB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/02 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/823437 (2013.01); H01L 27/088 (2013.01); H01L 29/0692 (2013.01); H01L 29/0696 (2013.01); H01L 29/4238 (2013.01); H01L 29/78 (2013.01); H01L 29/7835 (2013.01); H01L 29/41725 (2013.01); H01L 29/41758 (2013.01);
Abstract

A Metal Oxide Semiconductor (MOS) device formed on a substrate and a method for forming the MOS device. The MOS device includes a drain region, a gate region surrounding the drain region, source regions arranged around the gate region and across from the drain region, and bulk regions arranged around the gate region and separating the source regions. The gate region is formed in a loop around the drain region. In this manner, the on-resistance (Ron) of a MOS device is decreased without also increasing the area of the MOS device.


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