The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Mar. 12, 2015
Applicant:

Powerchip Technology Corporation, Hsinchu, TW;

Inventors:

Jian-Lin Chen, Kaohsiung, TW;

Ta-Chien Chiu, Miaoli County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H01L 21/76814 (2013.01);
Abstract

A method for fabricating semiconductor structure is provided. A substrate having a plurality of blocks is provided. Each of the blocks includes a first region and a second region. The first region and the second region are disposed alternately. A plurality of composite layers is formed on the substrate. The top-most layer of the composite layers is patterned. A plurality of composite blocks is formed on the first region of the substrate. The composite layers and the composite blocks on the blocks are removed successively by a removal process. A staircase structure is formed on the substrate.


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