The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2016
Filed:
Mar. 05, 2014
Applicant:
Kabushiki Kaisha Toshiba, Minato-ku, JP;
Inventors:
Assignee:
Kabushiki Kaisha Toshiba, Minato-ku, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 7/14 (2006.01); G11C 8/08 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 7/14 (2013.01); G11C 8/08 (2013.01); G11C 11/5621 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); H01L 27/11529 (2013.01); H01L 27/11536 (2013.01); H01L 27/11539 (2013.01); H01L 27/11541 (2013.01); G11C 2211/5641 (2013.01);
Abstract
According to one embodiment, a nonvolatile semiconductor storage device includes a word line transfer unit which transfers voltage applied to a memory cell selected on the basis of an address to a word line. The word line transfer unit includes a word line transfer transistor which is arranged in a first layout area of the word line transfer unit and transfers voltage applied to the memory cell to the word line and a dummy word line transfer transistor which is arranged in a second layout area provided outside an end of the first layout area and does not transfer voltage applied to the memory cell to the word line.