The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2016
Filed:
Oct. 25, 2013
Jae-hoon Jeong, Hwaseong-si, KR;
Won-cheol Lee, Seoul, KR;
Young-hoe Cheon, Suwon-si, KR;
Bo-sun Hwang, Yongin-si, KR;
Chan-seok Hwang, Seongnam-si, KR;
Jae-Hoon Jeong, Hwaseong-si, KR;
Won-Cheol Lee, Seoul, KR;
Young-Hoe Cheon, Suwon-si, KR;
Bo-Sun Hwang, Yongin-si, KR;
Chan-Seok Hwang, Seongnam-si, KR;
Abstract
A system for designing a semiconductor package using a computing system, comprising: a virtual stacking module configured to receive a layout parameter for a first chip, a layout parameter for a second chip, and a layout parameter for a package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate a plurality of virtual layouts in which the first and second chips are stacked, on the package substrate; a modeling module configured to model operating parameters for the first and second chips and the package substrate in response to the virtual layouts; and a characteristic analyzing module configured to analyze operating characteristics of the virtual layouts in response to the modeled operating parameters.