The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Apr. 09, 2013
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, JP;

Inventors:

Yoshiyuki Nakada, Kanagawa, JP;

Masayuki Ito, Kanagawa, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 21/78 (2013.01); G06F 9/50 (2006.01); G06F 12/02 (2006.01); G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1416 (2013.01); G06F 12/1441 (2013.01); G06F 21/78 (2013.01); G06F 9/30098 (2013.01); G06F 9/5016 (2013.01); G06F 12/0284 (2013.01);
Abstract

A memory protection circuit includes a memory access information register that stores memory access information related to memory areas which can be accessed by respective virtual machines, and an access determination circuit that determines whether to allow the virtual machines to access the memory areas based on a memory address when each of the virtual machines accesses a memory, information related to the virtual machines that access the memory, and the memory access information stored in the memory access information register. The memory access information register may comprise memory area setting registers and memory area allocation registers. A register access information register may indicate register areas which can be accessed by the virtual machines. A virtual machine scheduler or thread scheduler may determine an order of instructions to be executed.


Find Patent Forward Citations

Nakada, Yoshiyuki. (2016). Memory protection circuit, method and processing unit utilizing memory access information register to selectively allow access to memory areas by virtual machines (U.S. Patent No. 9465750). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9465750

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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