Memory system, method for controlling the same, and information processing device

Abstract

A memory system method for controlling the same, and an information processing device using the same are provided. The system includes a plurality of memory chips electrically connected with one another by a bus (e.g. address bus, data bus, control bus, etc.), which are disposed in a stacked arrangement and extend through the plurality of memory chips in a stacking direction, and a memory controller connected to a plurality of processors and to the bus, and further to a chip select signal line for outputting a chip select signal to each of the plurality of memory chips. The memory controller converts an address signal from each of the processors into a set of the chip select signal and the address signal, which is outputted to the address bus, so as to relay inputs and outputs of data between each of the processors and each of the memory chips.