The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2016
Filed:
Mar. 07, 2014
Applicant:
Vmware, Inc., Palo Alto, CA (US);
Inventors:
Rajesh Venkatasubramanian, San Jose, CA (US);
Puneet Zaroo, Santa Clara, CA (US);
Alexandre Milouchev, Brussels, BE;
Assignee:
VMware, Inc., Palo Alto, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 9/50 (2006.01); G06F 12/10 (2016.01); G06F 3/06 (2006.01); G06F 12/06 (2006.01); G06F 12/02 (2006.01); G06F 12/08 (2016.01);
U.S. Cl.
CPC ...
G06F 9/5083 (2013.01); G06F 9/5033 (2013.01); G06F 12/0891 (2013.01); G06F 3/0604 (2013.01); G06F 3/0614 (2013.01); G06F 3/0662 (2013.01); G06F 3/0665 (2013.01); G06F 12/0292 (2013.01); G06F 12/0638 (2013.01); G06F 12/0868 (2013.01); G06F 12/10 (2013.01); G06F 12/1009 (2013.01); G06F 12/1072 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/152 (2013.01); G06F 2212/2542 (2013.01);
Abstract
In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality.