The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Apr. 09, 2013
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, JP;

Inventors:

Hitoshi Suzuki, Kanagawa, JP;

Koji Adachi, Kanagawa, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 9/38 (2006.01); G06F 9/50 (2006.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/3009 (2013.01); G06F 9/38 (2013.01); G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06F 9/4881 (2013.01); G06F 9/5077 (2013.01); G06F 2209/5018 (2013.01);
Abstract

A semiconductor device includes an execution unit that executes an arithmetic instruction, and a scheduler including multiple first setting registers each defining a correspondence relationship between hardware threads and partitions, and which generates a thread select signal on the basis of a partition schedule and a thread schedule. The scheduler outputs a thread select signal designating a specific hardware thread, without depending on the thread schedule as the partition indicated by a first occupation control signal, according to a first occupation control signal output when the execution unit executes a first occupation start instruction.


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