The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Sep. 03, 2015
Applicant:

Dialog Semiconductor Gmbh, Kirchheim/Teck-Nabern, DE;

Inventors:

Dietmar Orendi, Frickenhausen-Linsenhofen, DE;

Biren Minhas, Bristol, GB;

Robert Baraniecki, Graz, AT;

Assignee:

Dialog Semiconductor GmbH, Kirchheim/Teck-Nabern, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/00 (2006.01); G05F 1/12 (2006.01); G01R 19/00 (2006.01); G01R 31/40 (2014.01); G01R 31/317 (2006.01); G01R 31/28 (2006.01); G05F 1/56 (2006.01);
U.S. Cl.
CPC ...
G01R 31/40 (2013.01); G01R 31/2834 (2013.01); G01R 31/31721 (2013.01); G05F 1/56 (2013.01);
Abstract

A circuit and method is described for automatically testing multiple LDO regulator circuits on an integrated circuit chip independent of an ATE. Each LDO regulator is tested for voltage at a specified current output capability, wherein the output driver transistor is formed by at least two pass transistors, which are each tested for voltage output at a particular current capability. The test results are delivered back to the ATE and for a failed test, the gate voltage of the pass device can be observed through an analog multiplexer to enable debug.


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