The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2016
Filed:
Jun. 18, 2014
Brocade Communications Systems, Inc., San Jose, CA (US);
Anil Mehta, Milpitas, CA (US);
Scott Kipp, Santa Barbara, CA (US);
Brocade Communications Systems, Inc., San Jose, CA (US);
Abstract
The PCS and FEC layers are combined into a single layer and the number of lanes is set at four lanes. The combination allows removal of many modules as compared to a serial arrangement of a PCS layer and an FEC layer. The reduction in the number of lanes, as compared to 100 Gbps Ethernet, provides a further simplification or cost reduction by further reducing the needed gates of an ASIC to perform the functions. Changing the lanes in the FEC layer necessitates changing the alignment marker structure. In the preferred embodiment a lane zero marker is used as the first alignment marker in each lane to allow rapid sync. A second alignment marker indicating the particular lane follows the first alignment marker.