The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2016
Filed:
Jun. 03, 2013
The Regents of the University of California, Oakland, CA (US);
Jingsheng J. Cong, Los Angeles, CA (US);
Bingjun Xiao, Los Angeles, CA (US);
The Regents of the University of California, Oakland, CA (US);
Abstract
A programmable logic circuit architecture using resistive memory elements. The proposed circuit architecture uses the conventional island-based Field Programmable Gate Array (FPGA) architecture, but with novel integration of CMOS-compatible resistive memory elements that can be programmed efficiently. In the proposed architecture, the programmable interconnects of FPGA are redesigned to use only resistive memory elements and metal wires. Then, the interconnects can be entirely fabricated over logic blocks to save area while keeping their architectural functions unchanged, and the programming transistors can be shared among resistive memory elements to save area. Finally, on-demand buffer insertion is proposed as the buffering solution to achieve more speedup.