The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2016

Filed:

Dec. 03, 2014
Applicant:

Tdk Corporation, Tokyo, JP;

Inventors:

Anuj Madan, Somerville, MA (US);

Dev V. Gupta, Concord, MA (US);

Zhiguo Lai, Acton, MA (US);

Assignee:

TDK Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03H 7/06 (2006.01); H03H 7/01 (2006.01); H03H 1/02 (2006.01); H03H 1/00 (2006.01);
U.S. Cl.
CPC ...
H03H 7/0161 (2013.01); H03H 1/02 (2013.01); H03H 7/06 (2013.01); H03H 2001/0014 (2013.01);
Abstract

Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.


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