The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2016

Filed:

Oct. 30, 2013
Applicant:

Rohm Co., Ltd., Kyoto-shi, Kyoto, JP;

Inventors:

Masashi Hayashiguchi, Kyoto, JP;

Mineo Miura, Kyoto, JP;

Kazuhide Ino, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 1/32 (2007.01); H03K 17/082 (2006.01); H03K 17/12 (2006.01); H03K 17/16 (2006.01); H02M 7/217 (2006.01); H03K 17/0412 (2006.01); H03K 17/0812 (2006.01); H02H 7/122 (2006.01); H02M 7/5387 (2007.01); H02M 1/088 (2006.01);
U.S. Cl.
CPC ...
H02M 1/32 (2013.01); H02M 7/217 (2013.01); H03K 17/04123 (2013.01); H03K 17/0822 (2013.01); H03K 17/08122 (2013.01); H03K 17/122 (2013.01); H03K 17/163 (2013.01); H02M 1/088 (2013.01); H03K 2217/0045 (2013.01);
Abstract

When an overcurrent is detected by an overcurrent detecting circuit (), a first switch circuit () selects a second input terminal (b) and connects an output terminal (c) to the second input terminal (b), with the result that the output terminal (c) of the first switch circuit () is put into a high-impedance state. The second switch circuit () selects a second output terminal (f) and connects an input terminal (d) to the second output terminal (f), with the result that the input terminal (d) of the second switch circuit () is grounded. That is, the gate of a first MOSFET () is grounded via a current interrupting resistor (). The resistance value of the current interrupting resistor () is set so that, at the time of a current interruption, a time interval from a time when the gate-source voltage or gate-emitter voltage of the switching device lowers to such a voltage that the temperature characteristics of the on-resistance of the switching device become negative to a time when the drain current or collector current of the switching device reaches 2% of the saturation current thereof is 500 [nsec] or less.


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