The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2016

Filed:

Feb. 14, 2014
Applicant:

Ps4 Luxco S.a.r.l., Luxembourg, LU;

Inventor:

Kanta Saino, Tokyo, JP;

Assignee:

PS4 LUXCO S.A.R.L., Luxembourg, LU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/108 (2006.01); G11C 11/408 (2006.01); H01L 27/02 (2006.01); G11C 11/4097 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10897 (2013.01); G11C 11/4085 (2013.01); G11C 11/4097 (2013.01); H01L 27/0207 (2013.01); H01L 21/76895 (2013.01); H01L 21/82345 (2013.01); H01L 27/10817 (2013.01); H01L 27/10852 (2013.01); H01L 27/10894 (2013.01);
Abstract

Disclosed embodiments relate to a semiconductor device having a plurality of unit transistors that include element isolation regions formed on a semiconductor substrate and a gate electrode formed in the shape of a frame and disposed on an active region sandwiched between the element isolation regions in such a way that the two ends of the outer periphery of the gate electrode extend onto the element isolation regions and the inner periphery thereof closes the active region. The active regions of unit transistors adjacent to one another in a first direction are electrically isolated from one another by means of the element isolation regions, and the active regions of unit transistors adjacent to one another in a second direction which intersects the first direction are linked to one another.


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